This application claims the priority of Korean Patent Application No. 10-2005-0014091, filed on Feb. 21, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device with a high operating current and a method of manufacturing the same.
2. Description of the Related Art
It is well known that the performance of a transistor largely depends on an operating current of the transistor. Accordingly, methods to obtain high operating current in transistors are continuously being studied. One such approach is referred to as strained silicon channel (SSC) technology, in which stress is applied to a channel region.
SCC technology provides a strained channel layer by forming a stress-applying layer on a metal oxide silicon field effect transistor (MOSFET). A description of SSC technology is disclosed in the article “A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistor” by T. Ghani et al., 2003, IEEE.
In general, layers that induce stress on a channel formed on a silicon substrate include a silicon germanium layer and a silicon nitride layer. An etch stop layer made of silicon nitride formed on a transistor that constitutes a semiconductor memory device, for example, a dynamic random access memory (DRAM), is used as a stress applying layer.
However, a stress applying layer (etch stop layer) made of silicon nitride that induces tensile stress increases mobility of an N-channel metal oxide semiconductor (NMOS) transistor but decreases mobility of a P-channel metal oxide semiconductor (PMOS) transistor. Accordingly, in a semiconductor memory device including both an NMOS transistor and the PMOS transistor, if the thickness of the etch stop layer made of silicon nitride is increased to improve the mobility of the NMOS transistor, the operating current of the NMOS transistor increases but the operating current of the PMOS transistor decreases, thereby failing to improve the operating currents of both type of transistors of the semiconductor memory device.
In the meantime, an applied stress layer that induces a compressive stress increases the mobility of the PMOS transistor but decreases the mobility of the NMOS transistor.
Further, if the thickness of the etch stop layer is increased, it is difficult to form self-aligned contact pads that are connected to source and drain regions in a memory cell region of the semiconductor memory device (e.g., DRAM).